opex

Description

Driver for MCU running custom GPIO expander firmware

Updating Registers

If changes are made to the device.yml file, the code can be updated using mrtutils

mrt-device -i doc/device.yml -o .

Usage

Configure GPIO

opex_t exp;

io_init_i2c(&exp, I2C1);            // Initialize expander on I2C1

io_gpio_cfg_t cfg;

cfg.mDIR = IO_GPIO_X_CFG_DIR_OUT;

io_cfg_gpio(&exp, 0, &cfg);         // Configure GPIO 0 to be an output

cfg.mDIR = IO_GPIO_X_CFG_DIR_IN;
cfg.mPP = 1;
cfg.mIRQ = IO_GPIO_X_CFG_IRQ_FALLING

io_cfg_gpio(&exp, 1, &cfg);        // Configure GPIO 1 to be an input with PUSH/Pull ON, and a falling trigger for IRQ

io_set_gpio(&exp, 1, LOW);         // Sets GPIO output to LOW. Since it is configured as an input, this enables the internal pulldown resistor

Set GPIO

io_set_gpio(&exp, 0, HIGH);       // Sets GPIO 0 High

Configure IRQ

io_cfg_irq(&exp, IO_IRQ_POLAR_LOW, 12)                            //Configure IRQ to pull GPIO 12 low when triggered

Register Map

Name

Address

Type

Access

Default

Description

GPIO_IN

0x00

uint32

R

0x00000000

Input values for gpio 0-25

GPIO_OUT

0x04

uint32

RW

0x00000000

Output values for gpio 0-15

GPIO_DDR

0x08

uint32

R

0x00000000

Direction Register for GPIO

IRQ_SRC

0x0C

uint32

R

0x00000000

latching Interrupt source mask. indicates souce of IRQ resets on read

ADC_0_VAL

0x10

uint16

R

0x0000

Output of ADC 0

ADC_1_VAL

0x12

uint16

R

0x0000

Output of ADC 1

ADC_2_VAL

0x14

uint16

R

0x0000

Output of ADC 2

ADC_3_VAL

0x16

uint16

R

0x0000

Output of ADC 3

ADC_4_VAL

0x18

uint16

R

0x0000

Output of ADC 4

PWM_0_VAL

0x1A

uint16

W

0x0000

PWM value for ch 0

PWM_1_VAL

0x1C

uint16

W

0x0000

PWM value for ch 1

PWM_2_VAL

0x1E

uint16

W

0x0000

PWM value for ch 2

PWM_3_VAL

0x20

uint16

W

0x0000

PWM value for ch 3

PWM_4_VAL

0x22

uint16

W

0x0000

PWM value for ch 4

PWM_5_VAL

0x24

uint16

W

0x0000

PWM value for ch 5

GPIO_0_CFG

0x26

uint8

RW

0x00

Configuration for GPIO 0

GPIO_1_CFG

0x27

uint8

RW

0x00

Configuration for GPIO 1

GPIO_2_CFG

0x28

uint8

RW

0x00

Configuration for GPIO 2

GPIO_3_CFG

0x29

uint8

RW

0x00

Configuration for GPIO 3

GPIO_4_CFG

0x2A

uint8

RW

0x00

Configuration for GPIO 4

GPIO_5_CFG

0x2B

uint8

RW

0x00

Configuration for GPIO 5

GPIO_6_CFG

0x2C

uint8

RW

0x00

Configuration for GPIO 6

GPIO_7_CFG

0x2D

uint8

RW

0x00

Configuration for GPIO 7

GPIO_8_CFG

0x2E

uint8

RW

0x00

Configuration for GPIO 8

GPIO_9_CFG

0x2F

uint8

RW

0x00

Configuration for GPIO 9

GPIO_10_CFG

0x30

uint8

RW

0x00

Configuration for GPIO 10

GPIO_11_CFG

0x31

uint8

RW

0x00

Configuration for GPIO 11

GPIO_12_CFG

0x32

uint8

RW

0x00

Configuration for GPIO 12

GPIO_13_CFG

0x33

uint8

RW

0x00

Configuration for GPIO 13

GPIO_14_CFG

0x34

uint8

RW

0x00

Configuration for GPIO 14

GPIO_15_CFG

0x35

uint8

RW

0x00

Configuration for GPIO 15

GPIO_16_CFG

0x36

uint8

RW

0x00

Configuration for GPIO 16

GPIO_17_CFG

0x37

uint8

RW

0x00

Configuration for GPIO 17

GPIO_18_CFG

0x38

uint8

RW

0x00

Configuration for GPIO 18

GPIO_19_CFG

0x39

uint8

RW

0x00

Configuration for GPIO 19

GPIO_20_CFG

0x3A

uint8

RW

0x00

Configuration for GPIO 20

GPIO_21_CFG

0x3B

uint8

RW

0x00

Configuration for GPIO 21

GPIO_22_CFG

0x3C

uint8

RW

0x00

Configuration for GPIO 22

GPIO_23_CFG

0x3D

uint8

RW

0x00

Configuration for GPIO 23

GPIO_24_CFG

0x3E

uint8

RW

0x00

Configuration for GPIO 24

GPIO_25_CFG

0x3F

uint8

RW

0x00

Configuration for GPIO 25

IRQ_CFG

0x40

uint16

RW

0x0000

IRQ Configuration

ADC_0_CFG

0x42

uint16

RW

0x0000

Configuration for ADC 0

ADC_1_CFG

0x44

uint16

RW

0x0000

Configuration for ADC 1

ADC_2_CFG

0x46

uint16

RW

0x0000

Configuration for ADC 2

ADC_3_CFG

0x48

uint16

RW

0x0000

Configuration for ADC 3

ADC_4_CFG

0x4A

uint16

RW

0x0000

Configuration for ADC 4

PWM_CONFIG

0x4C

uint32

RW

0x00000000

Configuration for PWM

WHO_AM_I

0x50

uint8

RW

0xAB

Device ID

VERSION

0x51

uint32

RW

0x00000000

Version of firmware

EEPROM_MEM

0x70

uint8

RW

0x00

Start address of EEPROM memory on stm8. User can read/write up to 128 bytes starting at this address

Registers

GPIO_IN

Address:

[0x00]

Input values for gpio 0-25

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Field

GPIO_IN

GPIO_OUT

Address:

[0x04]

Output values for gpio 0-15

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Field

GPIO_OUT

GPIO_DDR

Address:

[0x08]

Direction Register for GPIO

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Field

GPIO_DDR

IRQ_SRC

Address:

[0x0C]

latching Interrupt source mask. indicates souce of IRQ resets on read

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Field

IRQ_SRC

Fields

IRQ_SRC:

Source of IRQ

Name

Value

Description

GPIO_0

x01

IRQ triggered by GPIO0

ADC_0

x4000000

IRQ triggered by ADC0

ADC_1

x8000000

IRQ triggered by ADC1

ADC_2

x10000000

IRQ triggered by ADC2

ADC_3

x20000000

IRQ triggered by ADC3

ADC_4

x40000000

IRQ triggered by ADC4

ADC_n_VAL

Address:

[—-]

Output of ADC n

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Field

ADC_0_VAL

PWM_n_VAL

Address:

[—-]

PWM value for ch n

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Field

PWM_0_VAL

GPIO_n_CFG

Address:

[—-]

Configuration for GPIO n

Bit

7

6

5

4

3

2

1

0

Field

DIR

PP

LL

IRQ

ALT

EN

Flags

PP:

Enables Push/Pull on output, and Pull-up on input

ALT:

Indicates that GPIO is disabled because pin is being used for an alternate function (PWM, ADC, etc)

EN:

Enables GPIO

Fields

DIR:

Pin Direction

Name

Value

Description

IN

b0

GPIO is an input

OUT

b1

GPIO is an output
LL:

Low Level

Name

Value

Description

LOW

b0

Low level output

HIGH

b1
IRQ:

Interrupt selection

Name

Value

Description

NONE

b00

No interrupt

RISING

b01

Trigger on Rising

FALLING

b10

Trigger on falling

ANY

b11

Trigger on any

IRQ_CFG

Address:

[0x40]

IRQ Configuration

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Field

Enabled

Polarity

Output

Flags

Enabled:

Enables IRQ signal on selected GPIO

Fields

Polarity:

Sets polarity of IRQ

Name

Value

Description

ACTIVE_HIGH

b1

GPIO is high when IRQ is pending

ACTIVE_LOW

b0

GPIO is low when IRQ is pending
Output:

Selects the GPIO to use for IRQ

ADC_n_CFG

Address:

[—-]

Configuration for ADC n

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Field

Treshold

IRQ

EN

Flags

EN:

Enables ADC Channel

Fields

Treshold:

IRQ threshold for ADC channel

IRQ:

Interrupt setting for ADC channel

Name

Value

Description

NONE

b00

No interrupt

RISING

b01

Trigger on Rising

FALLING

b10

Trigger on falling

ANY

b11

Trigger on any

PWM_CONFIG

Address:

[0x4C]

Configuration for PWM

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Field

Period

Prescaler

CH7_Enable

CH6_Enable

CH5_Enable

CH4_Enable

CH3_Enable

CH2_Enable

CH1_Enable

CH0_Enable

Flags

CH0_Enable:

Enables PWM channel 0

CH1_Enable:

Enables PWM channel 1

CH2_Enable:

Enables PWM channel 2

CH3_Enable:

Enables PWM channel 3

CH4_Enable:

Enables PWM channel 4

CH5_Enable:

Enables PWM channel 5

CH6_Enable:

Enables PWM channel 6

CH7_Enable:

Enables PWM channel 7

Fields

Period:

Period for PWM signals

Prescaler:

Prescaler for PWM, using 16Mhz clock

Name

Value

Description

PRESCALER_1

b0000

divide clock by 1 (16Mhz)

PRESCALER_2

b0001

divide clock by 2 (8Mhz)

PRESCALER_4

b0010

divide clock by 4 (4Mhz)

PRESCALER_8

b0011

divide clock by 8 (2Mhz)

PRESCALER_16

b0100

divide clock by 16 (1Mhz)

PRESCALER_32

b0101

divide clock by 32 (500Khz)

PRESCALER_64

b0110

divide clock by 64 (250Khz)

PRESCALER_128

b0111

divide clock by 128 (125Khz)

PRESCALER_256

b1000

divide clock by 256 (62.5 Khz)

PRESCALER_512

b1001

divide clock by 512 (31.25 Khz)

PRESCALER_1024

b1010

divide clock by 1024 (1.5625 KHz)

PRESCALER_2048

b1011

divide clock by 2048 ()

PRESCALER_4096

b1100

divide clock by 4096 ()

PRESCALER_8192

b1101

divide clock by 8192 ()

PRESCALER_16384

b1110

divide clock by 16384 ()

PRESCALER_32768

b1111

divide clock by 32768 ()

WHO_AM_I

Address:

[0x50]

Default:

[0xAB]

Device ID

Bit

7

6

5

4

3

2

1

0

Field

Fields

ID:

ID of device

Name

Value

Description

STM8S003F3

x70

20 pin variant

STM8S003K3

x71

32 pin variant

VERSION

Address:

[0x51]

Version of firmware

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Field

MAJOR

MINOR

PATCH

BUILD

Fields

MAJOR:

Major Version

MINOR:

Major Version

PATCH:

Major Version

BUILD:

Major Version

EEPROM_MEM

Address:

[0x70]

Start address of EEPROM memory on stm8. User can read/write up to 128 bytes starting at this address

Bit

7

6

5

4

3

2

1

0

Field

EEPROM_MEM